The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device for outputting a read command applied being synchronized with an external clock signal as an output enable signal in synchronization with an internal clock signal corresponding to Column Address Strobe (CAS) latency information.
In general, a semiconductor memory device including a Double Data Rate Synchronous DRAM (DDR SDRAM) receives a read command from the outside in response to an external clock signal and outputs data stored inside to the outside in response to an internal clock signal. That is, in case of outputting the data, the data is processed by using the internal clock signal instead of the external clock signal inside the semiconductor memory device. Herein, since the read command is applied in synchronization with the external clock signal and the data is outputted in synchronization with the internal clock signal, the semiconductor memory device should include a circuit for synchronizing the read command, which is synchronized with the external clock signal, with the internal clock signal. The clock signal synchronized in view of the read command is changed from the external clock signal to the internal clock signal. Such an operation is generally called “domain crossing”.
Meanwhile, the semiconductor memory device domain-crosses the read command from the external clock signal to the internal clock signal and includes an output enable signal generation signal for generating an output enable signal according to CAS latency information. Since the output enable signal is a signal for securing operations for receiving the read command and outputting the data correspondingly to the external clock signal after CAS latency and is domain-crossed, it is synchronized with the internal clock signal. Generally, the CAS latency is stored in a mode resister set included in the semiconductor memory device and has information of whether the read command is applied per a unit time of one period of the external clock signal and the data is outputted correspondingly to nth external clock signal.
Meanwhile, the semiconductor memory device includes a Delay Locked Loop (DLL) for generating the internal clock signal and the output enable signal is synchronized with a DLL clock signal generated by the DLL.
FIG. 1 is a block diagram depicting an output enable signal generation circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the output enable signal generation circuit includes a counter reset signal generation unit 110, a reset unit 120, a DLL clock counting unit 130, an Output Enable (OE) delay replica model unit 140, an external counting unit 150, a counting value latching unit 160, and a counting value comparison unit 170.
The counter reset signal generation unit 110generates a first reset signal RSTb_DLL for resetting the DLL clock counting unit 130 by synchronizing a reset signal RSTb with a clock signal CLK_DLL.
The reset unit 120 supplies an initial counting value INT<0:2> corresponding to CAS latency CL to the DLL clock counting unit 130. Herein, the initial counting value INT<0:2> is described by employing a 3 bit code signal as one example. Initial counting values are set in the reset unit 120 correspond to CAS latency CL 3 to 6 and the initial counting values INT<0:2> outputted from the reset unit 120 corresponding to the initial counting set values are described in the following Table 1.
TABLE 1Initial countingCLset valueINT<2>INT<1>INT<0>35101441005301162010
For reference, the CAS latency CL, the initial counting set values corresponding to the CAS latency CL and the initial counting values INT<0:2> in Table 1 are changeable depending on a design.
The DLL clock counting unit 130 performs a counting operation in response to the first reset signal RSTb_DLL. That is, the DLL clock counting unit outputs a DLL clock counting value CNT_DLL<0:2> counted from the initial counting value INT<0:2> in response to the DLL clock signal CLK_DLL according to the first reset signal RSTb_DLL. For instance, if the initial counting set value INT<0:2> is set as 4 according to the CAS latency, the DLL clock counting unit 130 outputs the DLL clock counting value CNT_DLL <0:2> counted from 4 in response to the DLL clock signal CLK_DLL. Herein, the DLL clock counting unit 130 employs a general 3-bit counter as one example.
The OE delay replica model unit 140 outputs a second reset signal RSTb_EXT by delaying the first reset signal RSTb_DLL as modeling a delay degree between the DLL clock signal CLK_DLL and the external clock signal CLK_EXT. Herein, the OE delay replica model unit 140 has a similar construction to that of a DLL delay replica model unit (not shown in the drawing).
The external clock counting unit 150 performs a counting operation in response to the second reset signal RSTb_EXT. That is, it outputs an external clock counting value CNT_EXT<0:2> counted in response to the external clock signal CLK_EXT according to the second reset signal RSTb_EXT. The external clock counting unit 150, unlike the DLL clock counting unit 130, is set with an initial counting value of 0. In other words, after the second reset signal RSTb_EXT is activated, the external clock counting value CNT_EXT<0:2> is counted from 0 in response to the external clock signal CNT_EXT. Herein, the external clock counting unit 150, similar to the DLL clock counting unit 130, employs a general 3-bit counter as one example.
The counting value latching unit 160 latches the external clock counting value CNT_EXT<0:2> in response to a read command signal RD_EN and outputs it as the latched external clock counting value LAT_CNT<0:2>. Herein, the read command signal RD_EN is a pulse signal activated in response to the read command applied being synchronized with the external clock signal CLK_EXT.
The counting value comparison unit 170 compares the DLL clock counting value CNT_DLL<0:2> with the latched external clock counting value LAT_CNT<0:2> in order to output an output enable signal OE activated at a time when the two values are equal to each other. Herein, the output enable signal OE is a signal synchronized with the DLL clock signal CLK_DLL, i.e., the result obtained by synchronizing the read command applied after being synchronized with the external clock signal CLK_EXT with the DLL clock signal CLK_DLL. In other words, the read command becomes the output enable signal OE by being domain-crossed from the external clock signal CLK_EXT to the DLL clock signal CLK_DLL. At this time, the output enable signal OE is reflected by the CAS latency CL.
Herein, since specific circuit constructions for the counter reset signal generation unit 110,the reset unit 120, the DLL clock counting unit 130, the OE delay replica model unit 140, the external clock counting unit 150, the counting value latching unit 160, and the counting value comparison unit 170 are already widely known, the detail description thereof will be omitted.
FIG. 2 is a waveform diagram illustrating an operation timing of the output enable signal generation circuit shown in FIG. 1. For convenience of explanation, the case that the CAS latency CL is 4 is illustrated as “CL4”, the case that the CAS latency CL is 5 is illustrated as “CL5” and the case that the CAS latency CL is 6 is illustrated as “CL6”.
First of all, the case that the CAS latency CL is 4 will be described.
The initial counting value of the reset unit 120 is set with 4 according to Table 1. If the first reset signal RST_DLL is activated to logical ‘high’, the DLL clock counting unit 130 outputs the DLL clock counting value CNT_DLL<0:2> counted from 4 as the initial counting value in response to the DLL clock CLK_DLL.
Meanwhile, the OE delay replica model unit 140 outputs the second reset signal RSTb_EXT by reflecting a delay time D to the first reset signal RSTb_DLL. If the second reset signal is activated to logical ‘high’, the external clock counting unit 150 outputs the external clock counting value CNT_EXT<0:2> counted from 0 in response to the external clock signal CLK_EXT.
At this time, if the read command signal RD_EN is activated by receiving the read command RD, the counting latching unit 160 outputs an external clock counting value CNT_EXT<0:2> of 3 as a latched external clock counting value LAT_CNT<0:2>. The counting value comparison unit 170 compares the DLL clock counting value CNT_DLL<0:2> with the latched external clock counting value LAT_CNT<0:2> in order to activate the output enable signal OE at a time when the two values are equal to each other, i.e., the DLL clock counting value CNT_DLL<0:2> becomes 3. The semiconductor memory device has the thus-activated output enable signal OE and outputs data at a time of the external clock signal CLK_EXT of 4.
Semiconductor memory devices with high speed and low power consumption have been developed recently. However, the conventional output enable signal generation circuit has the following disadvantages in terms of high speed and low power consumption.
First of all, as an operation frequency of the semiconductor memory device increases, it is inevitable that the CAS latency CL increases. Since the counters constituting the DLL clock counting unit 130 and the external clock counting unit 150 are designed correspondingly to the CAS latency CL, if the CAS latency increases, the counters should be also designed to have more bits. When considering that the operation of a 4-bit counter is slower than that of a 3-bit counter, as the CAS latency CL increases, the counter is larger and the operation is slower. In addition, the counting value comparison unit 170 is also slower as the number of compared bits increases. These problems are elements retarding the high speed of the semiconductor memory device.
And, since the conventional output enable signal generation signal has a structure for latching the external clock counting value CNT_EXT<0:2> at a time when the read command signal RD_EN is activated, the DLL clock counting unit 130 and the external clock counting 150 should perform the counting operations at least before the read command signal RD_EN is activated. Specifically, before the read command is applied, the counter receiving the external clock signal CLK_EXT and the counter receiving the DLL clock signal CLK_DLL should perform counting operations continuously. This means that power is continuously consumed before the read command is applied, which increases power consumption.